Current IC capacitor designs utilize a two dimensional layout for the capacitor, which is an inefficient use of semiconductor real estate. The embodiments disclosed herein provide a method that forms the MIM capacitor in a three-dimensional format, thereby improving semiconductor real estate usage. For analog applications, typical capacitance would be in the range of 0.5 fF/sg.μm that is needed to support a breakdown voltage of 12V, thereby necessitating the need for a large area. Therefore, density improvement in capacitance will result in significant die size reduction.
Current capacitor designs use polysilicon as the bottom plate of the capacitor. With this approach, the breakdown distribution of the capacitor is significantly impacted by poly deposition, doping process and subsequent thermal anneals. In the disclosed embodiments, polysilicon is used only as a lead to the bottom plate of the capacitor. Thus, capacitor performance is not detrimentally impacted with poly deposition and doping conditions. The flexibility of the process, as well as the robustness is, therefore, much improved.